module rr_arbiter(
    input clk, rst_n,
    input READY0, READY1, READY2, READY3, 
    input READY4, READY5, READY6, READY7,
    output reg [7:0] GRANT// one-hot ,0000_0000 represents arbiter not working
);

reg  [7:0] current_prior;
wire [15:0] temp_grant;
wire [7:0] ready;
assign ready = {READY7, READY6, READY5, READY4, READY3, READY2, READY1, READY0};

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        current_prior <= 4'b0001;
    else
        current_prior <= {GRANT[6],GRANT[5],GRANT[4],GRANT[3],GRANT[2],GRANT[1],GRANT[0],GRANT[7]};
end

assign temp_grant = ~({ready, ready} - current_prior) & ({ready, ready});

assign GRANT = temp_grant[15:8] | temp_grant[7:0];

endmodule
